This invention relates to an addressing system for generating in a central processing unit of an electronic digital computer a working address from an instruction.
It is conventional when an instruction is read out for a central processing unit of an electronic digital computer from a memory that an instruction register is loaded with the instruction. A desired one of many general purpose registers is specified by a datum stored therefor in a data field of the instruction register. The working address is generated by combining the content of the specified general purpose register with the content of a relocation register to specify an address of the memory for reading out a datum stored in the specified address of the memory. The read-out datum is supplied either to the central processing unit for calculation or to another general purpose register for storage therein. Alternatively, the read-out datus is otherwise used.
In a sophisticated addressing system, use is made of only one relocation register loaded, at a time, with a certain number A. If the content of the specified general purpose register represents a number N, an address A+N is generated by usually calculating the sum of the contents. It is possible to either add one to the content of the specified general purpose register or subtract one therefrom to successively generate consecutive addresses for such a sum A+N. These addresses will be referred to as the addresses in a region of the address A. It is also possible to specify in the meantime another general purpose register loaded with another number S and thereby to generate a new address A+S. The content of the relocation register has to be changed when jump is required from the region of the address A to another region of a different address B. The change has been carried out by execution of the program. It has therefore been necessary to repeatedly change the content of the relocation register by the program when it is desired to alternatingly have access to the regions of the addresses A and B, such as in the order of addresses A+N, B+N, A+N+1, B+N+1, . . . . This has inevitably resulted in a reduction in the speed of operation. In addition, the repeated change lengthens the program. This means that a wider memory area is necessary for the program.
In a pamphlet published in 1977 by Zilog Inc., Calif., U.S.A., under the title of "Z80-CPU Technical Manual," use is taught of "Indexed Addressing" on pages 21-22. According to the teaching, two index registers are used in place of a single relocation register described hereinabove. One of the index registers is specified by the OP code of an instruction given to the central processing unit. The content of the specified index register is added to the displacement datum contained in the instruction to form a pointer to the memory. As described in the pamphlet, the indexed addressing simplifies the program when it is necessary to have access to two or more tables.
It is to be noted in connection with the indexed addressing that either of the index registers is specified independently of specification for the general purpose registers. This means that an additional program step is indispensable to specify the index register besides a program step for specifying a general purpose register. In other words, it is insufficient even by the use of the indexed addressing to shorten the program to a considerable extent and to do with a narrowest possible memory area.